NMIS-3000 input/output board
2x4"s[tm] 32 channel input, 32 channel output board, 74HC573 and 74HC574 based
The NMIS-3000 32-Bit In/32-Bit Out Card, in 2x4"s[tm] format, provides a JEDSTACK[tm] computer system with four 8-bit input and four 8-bit output lines. The lines are arranged to connect by two 34-conductor ribbon cables or by individual wires to 32 input points, 32 outputs points, with power and ground connections included.
- Four 8-bit parallel input ports
- Latchable inputs
- Four 8-bit parallel output ports
- Outputs latch processor written data
- Latch's output enable jumper/signal selectable
- Low power HCMOS design
- Compact size
- Easy connection
- Easy computer interfacing
Four 74HC373 octal latches are used as input gates, with optional externally-controlled latching. In one jumper setting, the latches are transparent, passing the input pins' current state directly to the processor. An active-low control signal can be used instead to latch the readings at that time. The readings will continue to be read in that state, despite any changes on the external input pins, until the control signal returns high again.
Four 74HC374 octal latches are used as output drivers, with optional externally-controlled enables. A similar jumper-or-signal user selection can determine if the latched output data is actively driven, or not.
A Vertical Stacking Connector in the lower right hand corner (top view) provides connections to the processor's address and data bus, control signals, 5V power and ground. Address decoding of the input chip's space in memory is accomplished by two octal comparators and 16 two-position jumpers. Each jumper setting corresponds to the state of a particular address line. The NMIS-3000 occupies four addresses. Any 4-byte boundary in the 64K address space of the JEDSTACK[tm] processor's bus can be selected by correct jumper placement.
The NMIS-3000 32-Bit In/32-Bit Out Card is designed to stack on the 2x4"s[tm] NMIS Series, the "100 Squared"[tm] NMIX and the "Generic Target Computer"[tm] NMIT Series (with the Vertical Stacking Connector added to the latter) of single board computers. The JEDSTACK[tm] provides interface signals to the board including address lines, data lines, control lines and 5V power and ground. The fast HC devices allow access times approaching 90nS.
The addressing of the octal drivers and latches on the NMIS-3000 is sensed by two 74HC688 (U1 and U2) octal comparators that decode the 14 address lines (A15 - A2) and one control line in order to select only four active locations out of a 64K address space.
The 74HC138 uses this signal for its negative enables and the output of Jumper "C" for its one positive enable. Jumper "C" will either provide a constant high if set for "80" type processors, or the "E" clock if set for 6500 and 6800 type processors. The "E" clock is necessary for correct timing information when using a 6500 or 6800 type processor on the JEDSTACK[tm] bus. If the processor is a 6500 or 6800 type (such as the F68HC11), the jumper should be in the "65" position. If the processor type is an 8031 or Z80 type (such as the 8052AH), the jumper should be in the "80" position.
The address inputs to the 74HC138 include two address lines (A0 and A1) and the R/W line. The four "read" decoded chip selects go to the input drivers. The four "write" decoded chip selects go to the output latches.
The 74HC245 acts as a bus buffers, limiting the load placed on the Data Bus to only one HC load (rather than eight). This increases the number of boards that can otherwise be put on the system, due to fan out limitations. By way of these bus drivers, the 74HC573's send data to the processor and the 74HC574's receive their data from the processor.
The center pin on Jumper "A" is the 74HC573's latch enable. When the line is high, the 74HC573's are transparent, passing the input pins' current state directly to the processor. Jumper "A" can be removed and an external signal provided to control the latch enable. When the line is high, the 74HC573's are transparent. When the line goes low the readings are latched at their state at the time. The readings will continue to be read in that state, despite any changes on the external input pins, until the line returns high again.
The center pin on Jumper "B" is the 74HC574's output enable. When the line is high, the 74HC574's are tri-stated. Jumper "B" can be removed and an external signal provided to control the output enable. When the line goes low the 74HC574's actively drive the output pins.