Cascaded + gated timers for measuring pulse width

[jinx]

Hi,

I'm trying to use the timers on the Servopod to read a high pulse width from a sensor. The pulse width duration is in the range from 500 microsecs to 6 secs. Which means I probably need a 128 prescalar on TimerB0, for eg and need to cascade TimerB1 so that I can read from uSecs to Secs.

I have tried to set TimerB0 for gated input but somehow it doesnt seem to be working. Once I get the timer to measure the high pulse(wait for high edge, time and latch on low edge) I then want to cascade the other timer so I can measure in secs also. Could anyone please direct me on how to do this with specific code examples (hopefully with some comments ) so that I can get this working?

Thanks in Advance.

I'm pasting the code I have here....this is from the adxl202.txt example online:

COLD
HEX

0D22 CONSTANT TB0.CAP
0D25 CONSTANT TB0.CNTR
0D26 CONSTANT TB0.CTRL
0D27 CONSTANT TB0.SCR

\ Initialize Timer B Module to do the gated counting.
: INIT_TIMERB
\ HEX
\ Init CTRL Register
7E00 TB0.CTRL !

\ Init SCR Register
0080 TB0.SCR !

\ Init CAP - Zero Capture registers
0000 TB0.CNTR !
\ DECIMAL
;

: TEST_TIMERB
CR
BEGIN
\ Wait for INPUT pin to go low
\ by checking SCR INPUT bit 8
TB0.SCR @ 0100 AND 0= IF
YELLED TOGGLE
INIT_TIMERB \ Zero counter for next time
TB0.CAP @ U. CR
\ S>F
\ 3.2E-04 F* 1E-02 F*
\ F. CR
ELSE
." ! "
THEN
?TERMINAL
UNTIL
;

[RMDumse]

Let's see how you are setting this Timer B0 up.

Here are all the possible modes


( CTRL
( BASE + 6
( 000 ( COUNT MODE NO COUNT
( 001 ( COUNT RISING EDGES OF PRIMARY SOURCE
( 010 ( COUNT RISING AND FALLING EDGES OF PRIMARY SOURCE
( 011 ( COUNT RISING EDGES OF PRIMARY SOURCE WHILE SEC. HIGH
( 100 ( QUADRATURE RISING EDGES OF PRIMARY AND SEC. SOURCE
( 101 ( COUNT PRIMARY SOURCE RISING EDGES, SEC. SPECS. DIRECTION
( 110 ( EDGE OF SEC. SOURCE TRIGGERS PRIMARY COUNT TILL COMPARE
( 111 ( CASCASE COUNTER MODE UP/DOWN
( 0000 ( Counter #0 input pin
( 0001 ( Counter #1 input pin
( 0010 ( Counter #2 input pin
( 0011 ( Counter #3 input pin
( 0100 ( Counter #0 output
( 0101 ( Counter #1 output
( 0110 ( Counter #2 output
( 0111 ( Counter #3 output
( 1000 ( PRIMARY COUNT SOURCE IP/1
( 1001 ( PRIMARY COUNT SOURCE IP/2
( 1010 ( PRIMARY COUNT SOURCE IP/4
( 1011 ( PRIMARY COUNT SOURCE IP/8
( 1100 ( PRIMARY COUNT SOURCE IP/16
( 1101 ( PRIMARY COUNT SOURCE IP/32
( 1110 ( PRIMARY COUNT SOURCE IP/64
( 1111 ( PRIMARY COUNT SOURCE IP/128
( 00 ( SECONDARY COUNT Counter # 0 input
( 01 ( SECONDARY COUNT Counter # 1 input
( 10 ( SECONDARY COUNT Counter # 2 input
( 11 ( SECONDARY COUNT Counter # 3 input
( 0 ( COUNT ONCE - 0 REPEATEDLY
( 1 ( COUNT ONCE - 1 ONCE AND STOP
( 0 ( COUNT LENGTH ROLL OVER
( 1 ( COUNT LENGTH COUNT UNTIL COMPARE AND REINITIALIZE
( 0 ( DIR COUNT UP
( 1 ( DIR COUNT DN
( 0 ( COINIT NO FORCE BY OTHER CHANNELS
( 1 ( COINIT FORCE BY OTHER COUNTER WHEN ACTIVE COMPARE
( 000 ( Active while counter is active, OUPUT MODE
( 001 ( CLEAR OFLAG OUTPUT ON SUCCESSFUL COMPARE
( 010 ( SET OFLAG OUTPUT ON SUCCESSFUL COMPARE
( 011 ( TOGGLE OFLAG OUTPUT ON SUCCESSFUL COMPARE
( 100 ( TOGGLE OFLAG USING ALTERNATING COMPARE REG
( 101 ( SET ON COMPARE, CLEAR ON SEC. SOURCE INPUT EDGE
( 110 ( SET ON COMPARE, CLEAR ON COUNTER ROLLOVER
( 111 ( ENABLE GATED CLOCK OUTPUT WHILE COUNTER IS ACTIVE

( STATUS
( BASE + 7
( 00 TCF, TCFIE
( 00 TOF, TOFIE
( 00 IEF, IEFIE
( 0 IPS
( 0 INPUT
( 00 CAPTURE DISABLED
( 01 CAPTURE REGISTER OPERATION CAP ON RISING EDGE IF IPS=0
( 01 CAPTURE REGISTER OPERATION CAP ON FALLING EDGE IF IPS=1
( 10 CAPTURE REGISTER OPERATION CAP ON FALLING EDGE IF IPS=0
( 10 CAPTURE REGISTER OPERATION CAP ON RISING EDGE IF IPS=1
( 11 CAPTURE REGISTER OPERATION CAP ON BOTH EDGE
( 0 MASTER
( 0 EEOF
( 0 VAL
( 0 FORCE
( 0 OPS
( 0 OEN


Now let's strip them down to what you've got: 7E00 and 0080


( 7E00
( 011 ( COUNT RISING EDGES OF PRIMARY SOURCE WHILE SEC. HIGH
( 1111 ( PRIMARY COUNT SOURCE IP/128
( 00 ( SECONDARY COUNT Counter # 0 input
( 0 ( COUNT ONCE - 0 REPEATEDLY
( 0 ( COUNT LENGTH ROLL OVER
( 0 ( DIR COUNT UP
( 0 ( COINIT NO FORCE BY OTHER CHANNELS
( 000 ( Active while counter is active, OUPUT MODE

( 0080
( 00 TCF, TCFIE
( 00 TOF, TOFIE
( 00 IEF, IEFIE
( 0 IPS
( 0 INPUT
( 10 CAPTURE REGISTER OPERATION CAP ON FALLING EDGE IF IPS=0
( 0 MASTER
( 0 EEOF
( 0 VAL
( 0 FORCE
( 0 OPS
( 0 OEN


Okay, so you have COUNT RISING EDGES OF PRIMARY SOURCE WHILE SEC. HIGH with IP/128 prescaling, or 3.2 uS per tick, with the secondary count pin being Counter # 0 input. Count REPEATEDLY, ROLL OVER, UP and 0 IPS with
CAPTURE REGISTER OPERATION CAP ON FALLING EDGE

Looks good.

In your code I notice you don't initialize the very first time, before the BEGIN UNTIL loop, and that may be the source of some of your trouble with this examples operation.

Oh, another thing, probably more important. You are looking at the actual input pin to see if it is high or low to know if you've had a capture. Yet you are not running with any predictable repeatability to see if the pulse has happened. For instance, if you get a result, you do a print. How long does the print take? How many times has the input line gone high and low while you were away printing? Plus, after you come back from printing, what if the line is still low? Do you print again anyway? Maybe you want to use one of the timer flags to determine capture.

Cascading isn't much trouble. Just set up another timer's input to be this one's output. Then count the overflows.

[nmitech]

Jinx,

Besure to change the System Base address as well. For ServoPod the TimerB is $1120. The example code you are using is for DSP805 & 803.

[jinx]

Hi,

Thanks to help from RMDumse and NmiTech, I've got the timer working and measuring pulse width from my motor sensor. Now I want to cascade two timers together to measure the full range of pulse durations (from 500 uS to 3 Secs).

I am currently using the Timer B0 with a 128 prescalar which gives me 3.2 uS per tick. This works fine for high RPMs but for low RPMs, I need to use 32 bits. For this I want to cascade Timer B1 to act as the higher order accumulator. So everytime B0 overflows (will happen every 209 mS currently), I want B1 to register an increment of 1 count. This way I can keep seconds counts.

The problem is that I can't get it to work at all. I read thru the manual and it seems all I have to do is to make the primary input of B1 to be the output of B0. I have kept the secondary input of B1 as 00. This does not seem to be working. I am pasting my code below:

COLD
DECIMAL

4384 CONSTANT TIMERB0.CMP1
4385 CONSTANT TIMERB0.CMP2
4386 CONSTANT TIMERB0.CAP
4388 CONSTANT TIMERB0.HOLD
4389 CONSTANT TIMERB0.CNTR
4390 CONSTANT TIMERB0.CTRL
4391 CONSTANT TIMERB0.SCR

4392 CONSTANT TIMERB1.CMP1
4393 CONSTANT TIMERB1.CMP2
4394 CONSTANT TIMERB1.CAP
4396 CONSTANT TIMERB1.HOLD
4397 CONSTANT TIMERB1.CNTR
4398 CONSTANT TIMERB1.CTRL
4399 CONSTANT TIMERB1.SCR

\ Initialize Timer B Module to do the gated counting and cascading.
: INIT_TIMERS

\ Init CTRL Register
\ 7E00 TIMERB0.CTRL !
32256 TIMERB0.CTRL !
\ Init SCR Register
\ 0080 TIMERB0.SCR !
128 TIMERB0.SCR !
\ Zero Capture registers
00 TIMERB0.CNTR !
\ Compare value for reiniting timer
0 TIMERB0.CMP2 !
10000 TIMERB0.CMP1 !


\ E800 TIMERB1.CTRL !
59392 TIMERB1.CTRL !
\ Init SCR Register
\ 0000 TIMERB1.SCR !
00 TIMERB1.SCR !
\ Zero Capture registers
00 TIMERB1.CNTR !
;

: TEST_TIMERS
CR
INIT_TIMERS
BEGIN
\ Wait for INPUT pin to go low
\ by checking SCR INPUT bit 8
TIMERB0.SCR @ 256 AND 0= IF
YELLED TOGGLE
INIT_TIMERS \ Zero counter for next time
\ 1E0
TIMERB0.CAP @ TIMERB1.HOLD @ U. U. CR
\ S>F
\ 3.2E-04 F* 2E-02 F*
\ F. CR
ELSE
." ! "
THEN
?TERMINAL
UNTIL
;

I have gone thru similar posts but what was done there was not clear to me
so i went from the manual. Could someone please let me know what I'm doing wrong with this? B0 works fine standalone but I need B1 to be cascaded as the higher-order store to get 32 bits accuracy.

One other thing: If I want B0 to re-init after comparing (say after counting to a 10000) it does not seem to do that either. It does capture the pulse and measures it well but does not seem to reinit on a compare.

Any help and explanations of the bits being set would be greatly appreciated.

Thanks in advance,
Jinx.