IsoPodV2 ADC error?

[pgruebele]

Hello,

I have an IsoPodV2 (non siwtching power supply).

Can anyone tell me how much noise I can expect on the ADC inputs given that analog ground and power are coupled to digital power?

Specifically, given the 12 bit value, how much error can I expect?

The DSP56F805 specs warn extensively that care must be taken in providing analog power and ground if you want reliable ADC readings. I looked at the IsoPod schematics but I'm not an anlog guy so I can't say how reliable analog power will be....

I have a variable resistor hooked up to power, gnd, and ANA0 on J2 and I am getting values ranging from 30544 to 30632. This is a spread of 88. Given that the ADC values are multiplied by 8 (12->15 bit), this means the actual spread is 88/8=11 which is a .15% error (12/4096*100/2). Does this seem right?

I have nothing else hooked up to the IsoPod (except serial cable and provided power supply).

Thanks

Philip Gruebele

[pgruebele]

Unfortunately, analog and digital power are directly coupled, so I cannot use a separate power support for VREF. Seems my only option is to add a much larger capacitor to existing capacitors on the power support. Currently it looks as though a 47uf exists. Since I need to make the circuit 10x more reliable perhaps I will try a 470uf cap in addition to the one that is already there...

Let me know what you think.

Thanks

Philip

[nmitech]

On the V2, remove the inductor L2 to seperate analog & digital power then connect the external power (VDDA) to pin 1, VREF and external GND to pin 2, VSSA.

[pgruebele]

Won't I have to disconnect analog ground also?

[pgruebele]

I put a 1500uf cap between analog power and ground on J2 and I still get the same results... Any recommendations?

[pgruebele]

I have tried removing L2 (green component to right of J2), and hooked up a VERY clean power supply and ground to J2 (2 1.5V batteries in series - it does not get any cleaner than that). Nothing is changed.

When I tie ANA0 to J2's power directly or via a 2.3K resitor, I still get the same jitter.

In fact, the only way I can make the jitter disappear is by tying ANA0 to J2's ground. In that case I get excatly 0 from the ADC. Once again, nothing's changed.

So, the noise is getting in through because analog and digital ground are connected or because or parasitic capacitance in the layout (or something else :-).

Please advise. A 12 bit ADC is not of much use if I can only use 8 high order bits reliably.

Can you try tying ANA0 to J2's analog power to see if you get the same error range?

Has anyone else used the ADC?

Thanks

Philip

[pgruebele]

Also, in the motorola docs it says that when doing single ended measurements, one should set VREF to be 100mV lower than the "minimum supply voltage the part is expected to see".

The IsoPod ties VRef directly to VDDA, so this is definitely not the case...

Philip

[g_jilek]

After you remove L2 use the hole next to J3 pin-8 for the positive leg of a 10.0uf Tantalum cap and tag the negitive leg to J3 pin-2. Do this on the bottom side of the board. This is the closest bypass that is easy to do for Vdda. There isn't much room here but also adding .1uf ceramic will a take a little more noise off the supply, but the 10.0uf does most of the bypassing, and adding it might be more hassle than it is worth.

You might try adding some hystersis to your circuit, either in code or in the analog circuit itself.

You may also need shielding to get much better. That last 1% is the toughest to get in any analog design.

Good luck

g_jilek

[pgruebele]

If I understand correctly, you are effectively telling me to replace L2 with a 10uf capacitor (in addition to using a separate power supply). I don't understand this. This couples analog and digital power via capacitor. Shouldn't I couple analog power to analog ground in order to reduce noise?

Thanks

Philip

[g_jilek]

By removing L2 you have disconnected VDDA from VDD. The L2 hole next J3-8 is connected to J3-1 VREF, this is also connected to VDDA. By putting the cap between VREF and VSSA ( J3-2 ) you have bypassed the ADC power supply. The grounds reference the digital and analog systems to each other and need to be connected.

g_jilek

[nmitech]

I agree with g_jilek,
After you remove L2 use the hole next to J3 pin-8 for the positive leg of a 10.0uf Tantalum cap and tag the negitive leg to J3 pin-2

or just tag the + and - lead of 10uF cap to J3 pin 1 and 2 respectively and bend the cap 90 degree angle similar position to the regulators, after you remove L2.

This does not couple analog and digital power.

[Dave]

Some additional thoughts are presented in using the ADC in the Motorola App Note 1947 at
http://e-www.motorola.com/brdata/PDFDB/docs/AN1947.pdf
I'm reading through it, attempting to see what applies to your situation.

[pgruebele]

I did this:

1. remove L2
2. attach 2 sequential 1.5v batteries to J3 pin 1 + 3
3. attach 470uf cap between J3 pin 1 + 3 (sorry that's all I have on hand).
4. attach 2.2K resistor from J3 pin 1 to ANA0

I still get considerable jitter - even more than before.

All this is directly connected to J3 - no long wires etc...

I don't have a scope so I'm afraid I cannot get a real view of what's going on, but nothing seems to work...

Wondering if anyone else has used the AD's successfully... I'm getting 4 bits of noise! Maybe something is wrong with my board or DSP?

Philip

[g_jilek]

The best test circuit would be to create a voltage divider with a potentiometer. A 1k pot will work here. Terminals 1 and 3 of the pot are connected in parallel with your battery and J3 pins 1 & 2; bat + connected to J3-1. The connection polarity to the pot terminals determines the rotation, ie. CW or CCW for increasing voltage at ANA0 (J3 pin 3). Pot terminal 2 is connected to ANA0. This setup will allow you to vary the voltage at ANA0 between zero and VDDA/VREF.

Dave's reference to Motorola App Note AN1947/D has a lot of application info that you will find useful. Also you might look at Chapter 9 of the Motorola DSP56F80x User's Manual. 9.7.5.1 will show you how to test the ADC.

g_jilek

[pgruebele]

Thanks,

Actually a pot is what I originally used because that is my actual application. I changed to the resistor directly connected to J3 just to remove any potential noise.

Both with the pot and resistor I get the same noise, so that does not help.

I will look at the Motorola app note, but I'm afraid I'm don't know what to do anymore.

I am looking to get a scope to hook up so I can verify that there really is noise...

Philip

[nmitech]

From motorola document below suggest that,
VREF must be equal to or less than VDDA and must be greater than 2.7V.
For optimal ADC performance, set VREF to VDDA-0.3V.

FYI, On IsoPod V2 board, you can seperate VDDA from VDD by removing L2. Also you can seperate VREF from VDDA by cutting the trace on the bottom size of J3 which is connecting from pin 1 to the L2 pin. After remove L2 and cutting trace, You can connect new VREF to pin 1 of J3 and VDDA source to L2 left pin, the one below pin 8 of J3.

More ADC electrical characteristics on page 37,
http://e-www.motorola.com/brdata/PDFDB/docs/DSP56F805.pdf

[g_jilek]

Philip

Do you need this accurcy across the entire span or are you trying to look a small part of that span. If the latter is the case you might consider putting an expanded scale front end on the input.

I setup and looked at what kind of jitter I was getting on my Pod. After right shifting back to 12-Bits I was getting +-3 counts, 0.15% error. If this is going to be a problem you will probably need to over sample and average. AN1947/D section 3.3 talks about this.

Good luck,

g_jilek

[pgruebele]

The Motorola specs say that typical ENOB (effective number of bits) for the DAC is 9 or 10. Currently I am at around 8, so I guess I am not that far off....


Does the IsoPod have a separate analog power and ground layer on the PCB?

I also wonder if the fact that VREF is ties to Analog pwoer could be a problem. The Motorola docs say that VREF should be VPPA-100mV for single ended applications....

Philip

[pgruebele]

After reading verious materials, I am now suspicious of the IsoPod analog grouinding scheme.

The first page of http://www-s.ti.com/sc/psheets/sbaa052/sbaa052.pdf as well as Motorola docs talk about proper grounding schemes and analog as well as digital ground layers on the PCB.

Can someone from NMI comment on the IsoPod design relative to that article. Based on the fact that nothing I have done seems to have helped it seems that a grounding issus could be causing the problem...

At this point, it might be eaier for me to deploy an external ADC chip via SPI, but of course I would greatly prefer using the IsoPod for this...


Thanks

Philip

[pgruebele]

Thanks for all your input.

I have finally settled on the solution:

1. oversample
2. hysterisis

This gives me much better results (+-1.5LSB).

I do, however, think that the next IsoPod version should look at analog grounding issues to see if AD accuracy can be improved.

Thanks again for all your help and suggestions...

Philip

[nmitech]

First, thanks pgruebele for the update on A/D test results.

Also I spent most of the day to test the IsoPod A/D against Motorola DSP56F805EVM board. It turned out IsoPod is doing alittle better on the percentage error compared with Motorola EVB board. The average % error on IsoPod is 0.15% which is +/- 3 counts, where motorola EVB board produced 0.19% error which is +/- 4 counts. The test results above used the onboard power supply, VDDA(VREF) & VSSA. With the 1K resistor pot connects on pin 1 & 3 to J3 pin 1 & 2 respectively. Center pin(2) of the resistor pot connects to ADC0, etc... There is no additional battery nor external power source , nor any extra filter cap used on this test.

We appreciated for your inputs to improve the A/D circuit and layout on the next design.

[pgruebele]

There must be something wrong with my IsoPod because I consistently get +-12 errors on the 12 bit value. That's 4x what others seem to be seeing..

My setup is identical to yours. +-3 or 4 would be great...

Philip

[RMDumse]

Here is what I use to take a time weighted average of the A/D reading in some of my IsoPod(TM) programs.

SCRUB ( CLEARS THE MEMORY

HEX

2VARIABLE RUN-AVE EEWORD
VARIABLE RUN# EEWORD 40 RUN# !

DECIMAL
1.0E0 FCONSTANT SCALE EEWORD
HEX

: INIT
2003 0E80 ! ( ASSIGN ADC CONTROL REG 1
003D 0E81 ! ( ASSIGN ADC CONTROL REG 2
3210 0E83 ! ( ASSIGN ADC CHANNEL LIST REG 1
7654 0E84 ! ( ASSIGN ADC CHANNEL LIST REG 2

0.0 RUN-AVE 2!
40 RUN# !
; EEWORD

: ANA0
E89 @ 8 / ( OUTPUT REGISTER FOR ADC CHANNEL ZERO
; EEWORD

: A/D
RUN-AVE 2@ D>F FDUP RUN# @ S>F F/ F-
F>D ANA0 S->D D+ RUN-AVE 2! ( running average
; EEWORD

: SMOOTH. RUN-AVE 2@ D>F RUN# @ S>F F/ SCALE F* F. ; EEWORD


( TEST WORD
( DISPLAYS THE VALUE OF ADC REGISTER VS. SMOOTHED
: Z DECIMAL BEGIN CR ANA0 . SMOOTH. ?TERMINAL UNTIL ; EEWORD

MACHINE-CHAIN ALL
A/D
( ...
( ...
END-MACHINE-CHAIN EEWORD

INIT EVERY 2000 CYCLES SCHEDULE-RUNS ALL ( KEEP ON REPEATING

[pgruebele]

Thanks for the Forth code. I am using the CodeWarrior C compiler so I cannot easily compare what we are doing. However, by taking 8 samples at a time and averaging them I get +-4 error on the 12 bit value.

[nmitech]

pgruebele,

Is it possible that you can email me, nmitech@newmicros.com your A/D test codewarrior program. I'd like to try it on my IsoPod and compare the results. I am not a C expert, so it would help alot if you have something already written. Thanks!

[RMDumse]

Originally posted by pgruebele
I am using the CodeWarrior C compiler so I cannot easily compare what we are doing.

Okay... well, just to describe it might not be too hard.

Basically you keep a running accumulator. Each sample time you divide the accumulator by some run value, in your case, say 8. The result of the division is 1/8th of the accumulator. Now subtract that part out of the accumulator. The accumulator has 7/8ths of its old value. That's like removing one of the averaged readings which made up the accumulator. Now add in the new reading to replace what you took out.

At any time you want a reading, take the accumulator divided by 8 and you have a time weighted average.

This system resists sudden changes and "jumpy" readings. Each new value can only modify 1/8th the total. Yet all the significant bits still accumulate. Step transistions resond quickly at first then slowly converged to the new value. It acts a bit like highly damped system. It's much easier to keep a large accumulator than retain a rotating array of past readings.

[pgruebele]

Yes, that's exactly what I am doing... and this gives me +-4 on the 12 bit value...

Thanks

Philip

[g_jilek]

Observed Noise on the IsoPod Analog Digital Converter

Beacuse my planned use of the IsoPod will utilize the Analog Inputs quite extensively, I undertook a bit of an indepth study of the reported noise.

Over the years I have always tended to over design my analog circuits. As a result I have had very few problems. When I got my IsoPod I didn't bother with a tight interface design. I had a box full of the wiring that was used in computer cases for the resets and LED's and the like. Handy little connectors that pluged directly onto the Pod. Anyway, when I did my first analog project I just soldered a couple of these wire sets to a pot and called it good. The analog was noisey, I didn't think anything of it, I just found a way to null out the noise and the circuit worked fine. So when this thread opened up I became intrigued by the issue.

Initially I used some of my eailer code that I had used to null out the jitter in my RC servo ADC Front End to observe the ADC converter. I could see how much the analog value was jumping around. At that point I constructed another analog pot interface using individually shielded twisted pair wiring with a 0.1uf ceramic cap on the power leads at the pot. The shields are terminated at the signel source, ie the pot. This
cable improved the error. After RMDumse posted his weighted average algorithm I modified it to convert the floating point value back to an integer and then began
testing different ADC configurations to see if any of them would improve the noise problem. The IsoPod that I was using for these tests was a stock V2 with linear
voltage regulators.

The results were interesting. The main source of the observed noise turned out to be coming from the computer monitor. This was mostly being injected through the serial programming cable. The measurements were taken with an oscillooscope at the terminals of the potentiometer. The computer was running throughout these tests. With the IsoPod powered down and the serial cable disconnected the noise density measured about 0.85mV, powering up the Pod this value went up to 2.0mV. Connecting the serial
cable and powering down the Pod the noise read 1.2mV, powering up the Pod this value went to 4.0mV. Replacing the shieled cabled pot with one that was unshieled, the noise density went 6.0mV. Both of these cabling setups were bypassed with a 10.0uf Tantalum capacitor at J3.

Testing of the operation of the ADC showed that the unshielded cable had an input error count of +/- 9 while the shielded cable's error count was +/- 4. I also noted
that running the converter in pulsed mode as apposed to looped tightened up the grouping; ie. more values in the middle, with the error remaining the same. Disabling
the sampling of unused inputs also helped. The smoothed error was also better with the converter running at max, 5Mhz. Another interesting note was that when the scope was hooked up I could see a +/-0.5 improvement in the smoothed value. The optimum
accumulator size was 16 to 32. This, using the shielded cable, produced a smoothed value of +/-0.5. A steady state was achieved with an accumulator of 80, 050 hex.

Conclusions: The ADC of the IsoPod V2, unmodified, is basically quite stable and predictable in any mode of operation that one would need to run it in. The slight
improvements that were observed would more than likly have little effect on operation. The use of some form of a weighted averaging algorithm, smoothing or hystersis is recommended to improve steady state performance. The most important improvement to the operation of the Analog Digital Converter is the use of a well designed and shielded interface.

Here is the code that I used for testing:

SCRUB

HEX

\ Analog Test Code

2VARIABLE RUN-AVG EEWORD
VARIABLE RUN# EEWORD \ Sets the Size of the Accumulator

DECIMAL
1.0E0 FCONSTANT SCALE EEWORD
HEX

: ADC_INIT ( -- ) \ Sets Up the Initial ADC Configuration
2000 0E80 ! \ Sets Start Bit & Once Sequential Scan Mode
0003 0E81 ! \ ADC Clock Period = IPbus/2N, N=DIV[3:0]+1
3210 0E83 ! \ Default Scan Order
7654 0E84 ! \ Default Scan Order
0002 0E85 ! \ Sample Disable Register, (Only Channel 0 is Scanned)

0.0 RUN-AVG 2!
20 RUN# !
; EEWORD

: STARTCNV ( -- ) \ Provides Start Pulse to Initiate an ADC Conversion
2000 0E80 ! ; EEWORD

: 8/ 2/ 2/ 2/ ; EEWORD ( n -- n ) \ Fast 8 /, Right Shift

: ANA0 ( -- n )
E89 @ 8/ ( OUTPUT REGISTER FOR ADC CHANNEL ZERO
; EEWORD

: A/D ( -- ) \ Calculates the Running Average of the Analog Input
RUN-AVG 2@ D>F FDUP RUN# @ S>F F/ F- F>D ANA0 S->D D+ RUN-AVG 2!
STARTCNV ; EEWORD

: SMOOTHED. ( -- ) \ Scales the Floating Point Value & Converts it to an Integer
RUN-AVG 2@ D>F RUN# @ S>F F/ SCALE F* FDUP F. \ Displays both Values
FROUND F>D DROP .
; EEWORD


( TEST WORD
( DISPLAYS THE VALUE OF ADC REGISTER VS. SMOOTHED - Floating Point & Integer
: TESTZ DECIMAL BEGIN CR ANA0 . SMOOTHED. ?TERMINAL UNTIL ; EEWORD

ADC_INIT

EVERY 2000 CYCLES SCHEDULE-RUNS A/D \ Keeps the Algorithm Running


g_jilek

[nmitech]

Great post, g_jilek! Thanks for the info.

[pgruebele]

Thanks for the info...

The only cable I used in my tests was the NMI serial cable (I assume it's shielded). I should probably have done a test where I disconnect this cable and accumulate my measurements with a stand alone IsoPod. Then I could rule out my laptop from injecting RF noise or serial port noise...

Anway

NMITech, were you able to run the C code I sent you? I 4 weeks I will have a scope, so I will also do a couple of tests to see where noise might be coming from in my case... Once again it seems that I am seeing much more noise than others...

Thanks


Philip

[nmitech]

pgruebele,

Sorry, I have not have a chance to try out your program yet. I am in the middle of upgrading my PC and my new PC does not have CW software install yet. I will keep you posted.

By the way, if you have not do any cut or modification on the board, you can call Sales Dept. at (214)339-2204
to exchange for a new one maybe it will help.

[g_jilek]

Here is a Motorola FAQ that explains how the ADC performance is characterized.

http://e-www.motorola.com/webapp/sps/utils/SingleFaq.jsp?FAQ-12313.xml

g_jilek