johnsmithx
03-02-03, 09:01 PM
The manual states the following:
'The total draw for the IsoPod™ under maximum speed is approximately 200 mA.
Sleeping or slowing the processor can substantially reduce current consumption.
The TD0 signal can shut down the RS-232 converter, saving about 30 mA, when not used for transmission, if the receiving unit will not sense this as noise.
The TD1 signal can shut down the RS-485 transceiver, U4, saving about 10 mA, when not used for transmission, if the other RS-485 receiving units will not sense this as noise. The other RS-485 transceiver, U3, cannot be shut down, but can be left uninstalled by arrangement with the factory.
Each digital pin is capable of sinking 4 mA and sourcing –4 mA. Each LED draws 1.2 mA when lit.'
The use of sleep modes is easy enough to figure, what I was curious about, was clock speed reduction, and how this is implemented. For example:
'The 68HC11 provides high performance at low power with supply voltages ranging from 3 V to 5.5 V. Further power reductions can be achieved by some devices which have a Phase-Locked Loop (PLL) clock synthesizer circuit. The PLL allows clock speed reduction by switching the internal clock to a lower, power-saving frequency. '
Since the ISOPOD has ample power for any reasonable applications I can imagine, I was wondering if there is an equivalent simple method by which I may reduce the clock speed of the ISOPOD controller, and what kind of current draw reduction might be achieved by this?
Basically, if I strip out everything I can, how low will this thing go in terms of net source draw? Lowering consumption is more important to me than flat out performance.
Thanks.
'The total draw for the IsoPod™ under maximum speed is approximately 200 mA.
Sleeping or slowing the processor can substantially reduce current consumption.
The TD0 signal can shut down the RS-232 converter, saving about 30 mA, when not used for transmission, if the receiving unit will not sense this as noise.
The TD1 signal can shut down the RS-485 transceiver, U4, saving about 10 mA, when not used for transmission, if the other RS-485 receiving units will not sense this as noise. The other RS-485 transceiver, U3, cannot be shut down, but can be left uninstalled by arrangement with the factory.
Each digital pin is capable of sinking 4 mA and sourcing –4 mA. Each LED draws 1.2 mA when lit.'
The use of sleep modes is easy enough to figure, what I was curious about, was clock speed reduction, and how this is implemented. For example:
'The 68HC11 provides high performance at low power with supply voltages ranging from 3 V to 5.5 V. Further power reductions can be achieved by some devices which have a Phase-Locked Loop (PLL) clock synthesizer circuit. The PLL allows clock speed reduction by switching the internal clock to a lower, power-saving frequency. '
Since the ISOPOD has ample power for any reasonable applications I can imagine, I was wondering if there is an equivalent simple method by which I may reduce the clock speed of the ISOPOD controller, and what kind of current draw reduction might be achieved by this?
Basically, if I strip out everything I can, how low will this thing go in terms of net source draw? Lowering consumption is more important to me than flat out performance.
Thanks.