Quad Quadrature Encoders with Index

[Pacetech]

Looking at http://www.newmicros.com/isopod/appnotes/TMR_QUAD_32%20BIT.txt - I see how to use the Timers to make 6 quadrature encoder inputs.

Actually it calls for 2 Channel 4's which I belive should be a Channel 4 (using Timer C0/C1) and Channel 5 (using timer D0/D1).

In any case, If I use the 2 built in quad encoders with INDEX input(Quad Timer Module) and then use Timer C0/C1 for a 3rd channel and Timer D0/D1 for my 4th, I still need to map inputs for the 2 INDEX inputs. Then I have to handle the index input in software.

Since I'm not using the HOME inputs, can I connect the INDEX from encoders 3 and 4 to those and generate a interrupt and then all I have to do is write a interrupt service routine to clear the interrupt and zero the encoder's counter register.

The ISR needs to be written in ASM.

Just wanted to make sure I'm heading down the right path.

Also, does anyone have an example of an ISR that I can look at?

[Pacetech]

OK, I've gotten 3 encoders to work with the index. I'm using the encoders as a user knob input, I initialize the 2 hardware quad encoders as follows:

: INITENC1 \ Hardware Quadrature decoder #0
0E40 2@ 0040 OR 0E40 2! ( Set bit 6 = XIP )
; EEWORD

: INITENC2 \ Hardware Quadrature decoder #1
0E50 2@ 0040 OR 0E50 2!
; EEWORD

XIP bit zeros the counter on an index pulse. I set the index

I used timer module 4 to do the 3rd encoder, initializing it as follows:

: INITENC4 \ Quadrature decoder using Timer D0/D1
( QUAD CH 4 MADE OUT OF TMRD0/1 AND INPUTS 0/1
8088 0D66 ! ( CTRL TMRD0 INA 0, INB 1
FFFF 0D60 ! ( CMP1 FOR OVERFLOW
0000 0D61 ! ( CMP2 FOR UNDERFLOW
0000 0D65 ! ( COUNTER
0000 0D67 ! ( STATUS

E800 0D6E ! ( CTRL TMRD1 EXTENDED 32 BITS
0000 0D6D ! ( COUNTER
0000 0D6F ! ( STATUS

2420 0D76 ! ( CTRL TMRD2 0010010000100000 rising edge count mode
( souce = index pin, length bit
0220 0D77 ! ( STATUS TMRD2 0000000000100000 - master bit
0001 0D70 ! ( Set CMP1 to 1 positive counts
FFFF 0D71 ! ( Set CMP2 to -1 = FFFF
0000 0D75 ! ( Initialize COUNTER
;


Basically uses quadrature counting of the 2 input pins. The index pin counts up or down, which gets a compare whenever I pass over the index the 2nd time. Can't figure out why I don't get the compare the first time it crosses the index, unless I count on all edges of the index.

The key is that I set the index to be the master( bit 5 - master mode), so when the index causes a compare, it re-initializes any channel that has been set for co-channel initialization, which channel 0 is.

So this is working fine, but now my challenge is to get a 4th quadrature decoder. Timer channel C only has 2 inputs, so I can't do the index using hardware.

Any ideas?

My last resort is to write an interrupt service routine for the index off some pin, but I haven't seen any examples of how to do an ISR and my assembly skills are rusty.

[RMDumse]

Originally posted by Pacetech
Actually it calls for 2 Channel 4's which I belive should be a Channel 4 (using Timer C0/C1) and Channel 5 (using timer D0/D1).


Yes, there is a one character typo in the comment where it says

( QUAD CH 4 MADE OUT OF TMRD0/1 AND INPUTS 0/1

and should say

( QUAD CH 5 MADE OUT OF TMRD0/1 AND INPUTS 0/1




Since I'm not using the HOME inputs, can I connect the INDEX from encoders 3 and 4 to those and generate a interrupt and then all I have to do is write a interrupt service routine to clear the interrupt and zero the encoder's counter register.


I suppose you could do that. I seldom have applications that require the INDEX input.



The ISR needs to be written in ASM. ...
Also, does anyone have an example of an ISR that I can look at?

I believe there is a section on this in the manual. Look at the CODE-INT word and the "Using CPU Interrupts in the IsoPod" section.

[RMDumse]

Originally posted by Pacetech
The key is that I set the index to be the master( bit 5 - master mode), so when the index causes a compare, it re-initializes any channel that has been set for co-channel initialization, which channel 0 is.

Very clever. These timer modules are very amazing in their flexibility and you've found an "unexpected" use for a third channel.

So this is working fine, but now my challenge is to get a 4th quadrature decoder. Timer channel C only has 2 inputs, so I can't do the index using hardware.

Any ideas?

Nothing comes to mind, if you must have a INDEX in.

Although, it would seem to me there are many options for clearing the register beyond just using machine code interrupts. If the encoders are hand operated, they likely aren't running that fast that a high level interrupt, or even a scheduled service routine couldn't get them.

[Pacetech]

Well, I'm trying the ISR route - but V.060 won't work - any way to get v0.61??

[nmitech]

To get V0.61, here is your options,

- If you have a JTAG-Cable-10P, you can sign the IsoMax license agreement,
http://www.newmicros.com/cgi-bin/store/order.cgi?form=prod&cat=isomax
We will email you the New Srecord to upgrade.

- or Email to nmiproduction@newmicros.com to request for a RMA # and instruction to return for free upgrade.

[Pacetech]

Originally posted by nmitech
To get V0.61, here is your options,


I Got the v0.61, works great.

Are there any other differences in .61 other than the PF! fix for the ISR vectors?

[nmitech]

Just it! Please check your email.

[Pacetech]

Ok, everything seems to be working, except I cannot find the opcodes for this processor.

Can anyone tell me what this would loook like?

BFSET #$8000,X:$0E40

I know
BFCLR #$8000,X:$0E40 would compile to

80F4 P, 0E40 P, 8000 P,

But I can't find what BFSET would comple to. I tried to use the assembler, but I get errors.

[petegray]

BFSET #$8000,X:$0E40 looks like this ...

82F4 0E40 8000

-Pete.

[Pacetech]

Originally posted by petegray
BFSET #$8000,X:$0E40 looks like this ...

82F4 0E40 8000

-Pete.

Thanks. I finally figured out what that crazy "DSP56F805 Instruction Encoding" document was for.

[petegray]

No problem. It's a complex instruction set. It may be quicker to email me directly (petegray@ieee.org) if you need any other translations. I'll just run it through the "full blown" assembler and email you the opcodes.

Regards,
-Pete.